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STK6006
DATA SHEET
by
SYNTEK(R)
=========STK6006=========
.com 8051 Embedded LCD Monitor Micro-Controller
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Version 1.0
DESIGN CENTER 6F, YU FENG BLDG. 317 SUNG-CHANG RD., TAIPEI, TAIWAN, R.O.C. TEL: 886-2-2505-6383 FAX: 886-2-2506-4323
HEADQUARTER 3F, NO.24-2, INDUSTRY E.RD., IV, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5773181 FAX: 886-3-5778010
(c) Co Copyright SYNTEKT SEMICONDUCTOR Corporation Licensors (2000). All rights reserved .compyright SYNTEKT SEMICONDUCTOR Corporation & Licensors (2000). All rights reserved 1
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(c) Copyright SYNTEKT SEMICONDUCTOR Corporation & Licensors (2000). All rights reserved
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STK6006
Caution!
The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this data sheet. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy, or fitness for any particular part of this document. In no event DCNT the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this data sheet or product. Product names appearing in this data sheet are for identification purpose only, and trademarks and product names or brand names appearing in this document are property of their respective owners. This data sheet contains materials protected under International Copyright Laws. All rights reserved. No part of this data sheet may be reproduced, transmitted, or transcribed without the expressed written permission of the manufacturer and authors of this data sheet.
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STK6006 STK6006 Data Sheet Table of Contents Item Page 1. GENERAL DESCRIPTION........................................................................... 5 2. FEATURES .................................................................................................... 5 3. BLOCK DIAGRAM ...................................................................................... 5 4. PIN CONNECTION....................................................................................... 6 5. PIN CONFIGURATION ................................................................................ 7 6. POWER CONFIGURATION......................................................................... 7 7. PINS DESCRIPTION .................................................................................... 8 8. FUNCTIONAL DESCRIPTIONS ................................................................. 9 8.1 8051 CPU Core ...................................................................................... 9 8.2 Allocation of Memory ............................................................................ 9 8.2.1 Internal Special Function Registers (SFR).................................. 9 8.2.2 Internal RAM .............................................................................. 9 8.2.3 Auxiliary RAM (AUXRAM) ...................................................... 9 8.2.4 Dual Port RAM (DDCRAM) ...................................................... 9 .com 8.2.5 External Special Function Registers (XFR) ................................ 9 8.3 Chip Configuration................................................................................. 10 8.4 I/O Port ................................................................................................... 13 8.4.1 Port 1 ........................................................................................... 13 8.4.2 P3.0-2, P3.4-5.............................................................................. 13 8.4.3 Port 4, Port 5, and Port 6 ............................................................. 13 8.5 PWM DAC ............................................................................................. 14 8.6 HSYNC/VSYNC Processing ................................................................. 15 8.6.1 H/V Frequency Counter .............................................................. 15 8.6.2 Composite SYNC Separation/Insertion ...................................... 16 8.6.2.1 Horizontal Frequency table ............................................ 16 8.6.2.2 Vertical Frequency table................................................. 16 8.6.3 Output HBLANK/VBLANK Control and Polarity Adjustment . 16 8.6.4 Detection of H/V Polarity............................................................ 17 8.6.5 Self-Test Pattern Generator ......................................................... 17 8.6.6 Real-Time Check on H/V ............................................................ 18 8.6.7 VSYNC Interrupt ........................................................................ 18 8.6.8 HSYNC Clamp Pulse Output ...................................................... 18 8.6.9 H/V SYNC Processor Register.................................................... 18
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STK6006 8.7 DDC&I2C Interface ............................................................................. 22 8.7.1 SlaveB Block ............................................................................... 22 8.7.2 DDC1/DDC2x Mode, DDCRAM, and SlaveA Block ................ 23 8.7.3 I2C Function Block in Master Mode........................................... 23 8.7.3.1 To read the I2C Device..................................................... 23 8.7.3.2 To write the I2C Device ................................................... 24 8.8 A/D Converter ...................................................................................... 26 8.9 Low Power Reset (LVR) & Watching Timer ....................................... 27 8.10 In-System Programming Function (ISP)............................................ 28 8.10.1 ISP Control Block........................................................................ 28 8.10.2 Start to ISP Data Write/Read ....................................................... 29 8.10.3 Cyclic Redundancy Check (CRC)............................................... 30 9. MEMORY MAP of XFR................................................................................ 31 10. ELECTRICAL PARAMETERS................................................................... 33 10.1 DC Characteristics................................................................................ 33 10.2 AC Characteristics................................................................................ 33 10.3 Absolute Maximum Ratings................................................................. 33 .com 10.4 Operating Conditions Allowable.......................................................... 33 11. PACKAGE DIMENSION ............................................................................ 34 11.1 40-Pin PDIP 600 Mil ............................................................................ 34 11.2 42-Pin SDIP Unit .................................................................................. 34 11.3 44-Pin PLCC Unit .................................................................................. 35 12. INFORMATION........................................................................................... 35 12.1 Order Information................................................................................. 35 12.2 Contact Information ............................................................................. 35
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STK6006 1. GENERAL DESCRIPTION
The STK6006, an LCD monitor controller, is an embedded device with 8051 CPU core, which is in particularly designed for application to an LCD Monitor. It consists of an 8051 CPU core, a 1024-byte SRAM, 14 built PWM DACs, a VESA DDC interface, a 4-channel A/D converter, and a 64k-byte internal program Flash ROM. STK6006 works with both 5V/3.3V power supply and I/O, and 3.3V core operating voltage.
2. FEATURES
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14 channels of PWM DAC (max.) 31 I/O pins (max.) 8051 core, available for operating frequency at 12MHz with double CPU clock F/W optional 1024 bytes of RAM; 64K bytes of program Flash ROM support In-System Programming function (ISP) 5V/3.3V power supply and I/O; 3.3V core operating voltage Built-in self-test pattern generator with programmable free-running timing (15 -150KHz) .com Built-in lower power reset circuit SYNC processor for composite separation/insertion, H/V polarity/frequency check, and polarity adjustment Single master I2C interface for internal device to communicate Two slave I2C addresses; H/W auto-transfer DDC1/DDC2x data Feature corresponding to VESA DDC1/2B/2Bi/2B+ 4 channels of 6-bit ADC (max.) A selection to protection from the Flash ROM program code Watchdog timer featuring programmable interval Package designed with 40-pin DIP, 42-pin SDIP, or 44-pin PLCC
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3. BLOCK DIAGRAM
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STK6006 4. PIN CONNECTION
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STO/P4.2 P6.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8 DA9 HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 RST P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 NC NC RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STO/P4.2 P6.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8 DA9 HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 P1.6 P1.5
40 Pin PDIP
31 30 29 28 27 26 25 24 23 22 21
42 Pin SDIP
32 31 30 29 28 27 26 25 24 23 22
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DA0/P5.0 DA1/P5.1 DA2/P5.2 DA3/P5.3
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DA4/P5.4 DA5/P5.5
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VSYNC
HSYNC
VDD3 4
NC 6 RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STO/P4.2 P6.2/AD2 P1.0 7 8 9 10 11 12 13 14 15 16 17 18 P1.1
NC 5 19 P3.2/INT0
3 21 P1.3
2 22 P1.4
44 Pin PLCC
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44
43
42
41
40 39 38 37 36 35 34 33 32 31 30 29 DA8 DA9 HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.7/DA13 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd
20 P1.2
23 P1.5
24 P1.6
25 P1.7
26 P6.1/AD1
27 P6.0/AD0
28 HSDA/P3.1/Txd
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STK6006 5. PINS CONFIGURATION
"Open drain pin" means the pin may sink at least 4mA current but drive only 10~20uA to VDD. It may be used as input or output function and needs an external pull-up resistor. "CMOS output" means the pin may sink at least 4mA and drive. It is not preferred to use such pin as input function. "8051 standard pin" is a pseudo-open drain pin. It may sink at least 4mA current when output stays at a low level, and drives at least 4mA current for 2 X'tal period when output changes from a low level to a high level, and then drives at 120A for a high level. It can be used as input or output function and needs an external pull-up resistor when driving a device with heavy load.
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6. POWER CONFIGURATION
The STK6006 works in a system with a 5V or 3.3V power supply. In a 5V-power system, the VDD pin is connected to a 5V power supply and the VDD3 is connected to external capacitor; all output pins changes from 0 to 5V, and input pins can accept a voltage ranging from 0 to 5V. The voltage range of ADC conversion is 5V. However, the X1 and X2 pins operating below 3.3V. In a 3.3V power system, VDD and VDD3 are connected to 3.3V power, all output pins change from 0 to 3.3V, HSYNC, VSYNC and open drain pin may allow input ranging from 0 to 5V, and other input pins only allow input ranging from 0 to 3.3V. The voltage range of ADC conversion is 3.3V.
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STK6006 7. PINS DESCRIPTION
40 pins DA0/P5.0 3 DA1/P5.1 2 DA2/P5.2 1 DA3/P5.3 38 DA4/P5.4 37 DA5/P5.5 36 DA6/P5.6 30 DA7/HCLAMP 31 DA8 35 DA9 34 P1.0 13 P1.1 14 P1.2 16 P1.3 17 P1.4 18 P1.5 19 P1.6 20 P1.7 21 P6.0/AD0 23 P6.1/AD1 22 P6.2/AD2 12 P6.3/AD3 P6.4/DA10 26 P6.5/DA11 27 P6.6/DA12 28 P6.7/DA13 VDD3 4 VDD 5 VSS 6 VBLANK/P4.0 32 HBLANK/P4.1 33 X2 7 X1 8 RST 29 ISDA/P3.4/T0 9 ISCL/P3.5/T1 10 HSCL/P3.0/Rxd 25 HSDA/P3.1/Txd 24 P3.2/INT0 15 HSYNC 39 VSYNC 40 STO/P4.2 11 Name Pin No. 42 pins 3 2 1 40 39 38 32 33 37 36 16 17 19 20 21 22 23 24 26 25 15 29 30 31 4 8 9 34 35 10 11 7 12 13 28 27 18 41 42 14 44 pins 3 2 1 42 41 40 34 35 39 38 17 18 20 21 22 23 24 25 27 26 16 9 30 31 32 33 4 8 10 36 37 11 12 7 13 14 29 28 19 43 44 15 I/O Type Description
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I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) I/O PWM DAC output / General purpose I/O (CMOS) O PWM DAC output / Hsync clamp pulse output (CMOS) O PWM DAC output (open drain) O PWM DAC output (open drain) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) I/O General purpose I/O (CMOS output or 8051 standard) .com I/O General purpose I/O / ADC Input (CMOS) DataShee I/O General purpose I/O / ADC Input (CMOS) I/O General purpose I/O / ADC Input (CMOS) I/O General purpose I/O / ADC Input (CMOS) I/O General purpose I/O / PWM DAC output (CMOS) I/O General purpose I/O / PWM DAC output (CMOS) I/O General purpose I/O / PWM DAC output (CMOS) I/O General purpose I/O / PWM DAC output (CMOS) O 3.3V core power 5V or 3.3V Positive Power Supply Ground O Vertical blank / General purpose Output (CMOS) O Horizontal blank / General purpose Output (CMOS) O Oscillator output I Oscillator input I Active-high reset I/O Master I2C data / General purpose I/O / T0 (open drain) I/O Master I2C clock / General purpose I/O / T1 (open drain) I/O Slave I2C clock / General purpose I/O / Rxd (open drain) I/O Slave I2C data / General purpose I/O / Txd (open drain) I/O General purpose I/O / INT0 (8051 standard) I Horizontal SYNC or Composite SYNC Input I Vertical SYNC input O Self-test video output / General purpose Output (CMOS)
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STK6006 8. FUNCTIONAL DESCRIPTIONS
8.1 8051 CPU Core The CPU core of STK6006 is compatible to 8051 industry standard, it consists of 256 bytes of RAM, special function registers (SFR), two timers, five interrupt sources, and a serial interface. The CPU core catches its program code from a 64K-byte Flash in STK6006. In addition, it uses the port0 and port2 to access an external special function register (XFR) and an external auxiliary RAM (AUXRAM). When CPUclk is set, the CPU core can work at double rate. And then the CPU operates as if a 24-MHz crystal is applied to STK6006, but I2C, DDC, and the H/V processor still work at the original frequency. Note: Listed in this data sheet, all registers are collected in the external RAM area of 8051. You may refer to the 8051 specifications for an internal RAM memory map in detail. 8.2 Allocation of Memory 8.2.1 Internal Special Function Registers (SFR)
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The SFR are the same as the 8051 standard. 8.2.2 Internal RAM
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The 256 bytes of internal RAM kept in STK6006 are the same as the 8052 standard. 8.2.3 Auxiliary RAM (AUXRAM) Total 512 bytes of auxiliary RAM is configured in the 8051 external RAM area 800h - 9FFh. Programs can use the "MOVX" instruction to access the AUXRAM. 8.2.4 Dual Port RAM (DDCRAM) 256 bytes of a Dual Port RAM is configured in the 8051 external RAM area E00h - EFFh. Programs can use the "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC02 EEPROM is connected to the interface. 8.2.5 External Special Function Registers (XFR) The XFR is a group of registers configured in the 8051 external RAM area F00h - FFFh for the special functions. Programs can use the "MOVX" instruction to access these registers.
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FFh Internal RAM Accessible by indirect addressing only (Using MOV A,@Ri instruction) 80h 7Fh SFR Accessible by direct addressing
FFFh XFR Accessible by indirect external RAM addressing (Using MOVX instruction) DDCRAM Accessible by indirect external RAM addressing (Using MOVX instruction) AUXRAM Accessible by indirect external RAM addressing (Using MOVX instruction
EFFh
F00h Internal RAM Accessible by direct and indirect addressing
E00h 9FFh
00h
800h
8.3 Chip Configuration The Chip Configuration registers explain the chip configuration and the pin function.
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Reg. Name PADOPT PADOPT PADOPT PADOPT PADOPT PADOPT OPT
Addr. Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 F50h(w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E F51h(w) P56E P55E P54E P53E P52E P51E F52h(w) HI2CE II2CE HCLPE P42E P41E F53h(w) P56oe P55oe P54oe P53oe P52oe P51oe F54h(w) P67oe P66oe P65oe P64oe P63oe P62oe P61oe F55h(w) P17co P16co P15co P14co P13co P12co P11co F56h(w) PWMf PWMd CPUclk HSCLlo MI2CS MI2CF1
Bit 0 AD0E P50E P40E P50oe P60oe P10co MI2CF0
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PADOPT (w): control registers in a pad mode, all standing for "0" in Chip Reset DA13E = 1 Pin "P6.7/DA13" for DA13 = 0 Pin "P6.7/DA13" for P6.7 DA12E = 1 Pin "P6.6/DA12" for DA12 = 0 Pin "P6.6/DA12" for P6.6 DA11E = 1 Pin "P6.5/DA11" for DA11 = 0 Pin "P6.5/DA11" for P6.5 DA10E = 1 Pin "P6.4/DA10" for DA10 = 0 Pin "P6.4/DA10" for P6.4 AD3E = 1 Pin "P6.3/AD3" for AD3 = 0 Pin "P6.3/AD3" for P6.3
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STK6006
AD2E = 1 Pin "P6.2/AD2" for AD2 = 0 Pin "P6.2/AD2" for P6.2 AD1E = 1 Pin "P6.1/AD1" for AD1 = 0 Pin "P6.1/AD1" for P6.1 AD0E = 1 Pin "P6.0/AD0" for AD0 = 0 Pin "P6.0/AD0" for P6.0 P56E = 1 Pin "DA6/P5.6" for P5.6 = 0 Pin "DA6/P5.6" for DA6 P55E = 1 Pin "DA5/P5.5" for P5.5 = 0 Pin "DA5/P5.5" for DA5 P54E = 1 Pin "DA4/P5.4" for P5.4 = 0 Pin "DA4/P5.4" for DA4 P53E = 1 Pin "DA3/P5.3" for P5.3 = 0 Pin "DA3/P5.3" for DA3 P52E = 1 Pin "DA2/P5.2" for P5.2 = 0 Pin "DA2/P5.2" for DA2
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P51E = 1 Pin "DA1/P5.1" for P5.1 = 0 Pin "DA1/P5.1" for DA1 P50E = 1 Pin "DA0/P5.0" for P5.0 = 0 Pin "DA0/P5.0" for DA0
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HI2CE = 1 Pin "HSCL/P3.0/Rxd" for HSCL; pin "HSDA/P3.1/Txd" for HSDA = 0 Pin "HSCL/P3.0/Rxd" for P3.0/Rxd; pin "HSDA/P3.1/Txd" for P3.1/Txd II2CE = 1 Pin "FORDA/P3.4/T0" for FORDA; pin "FORCL/P3.5/T1" for FORCL = 0 Pin "FORDA/P3.4/T0" for P3.4/T0; pin "FORCL/P3.5/T1" for P3.5/T1 HCLPE = 1 Pin "DA7/HCLAMP" for HSYNC clamp pulse output = 0 Pin "DA7/HCLAMP" for DA7 P42E = 1 Pin "STO/P4.2" for P4.2 = 0 Pin "STO/P4.2" for STO P41E = 1 Pin "HBLANK/P4.1" for P4.1 = 0 Pin "HBLANK/P4.1" for HBLANK. P40E = 1 Pin "VBLANK/P4.0" for P4.0. = 0 Pin "VBLANK/P4.0" for VBLANK. P56oe = 1 P5.6 used as output pin. = 0 P5.6 used as input pin. P55oe = 1 P5.5 used as output pin. = 0 P5.5 used as input pin.
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P54oe = 1 P5.4 used as output pin.
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STK6006
= 0 P5.4 used as input pin. P53oe = 1 P5.3 used as output pin. = 0 P5.3 used as input pin. P52oe = 1 P5.2 used as output pin. = 0 P5.2 used as input pin. P51oe = 1 P5.1 used as output pin. = 0 P5.1 used as input pin. P50oe = 1 P5.0 used as output pin. = 0 P5.0 used as input pin. P67oe = 1 P6.7 used as output pin. = 0 P6.7 used as input pin. P66oe = 1 P6.6 used as output pin. = 0 P6.6 used as input pin. P65oe = 1 P6.5 used as output pin. = 0 P6.5 used as input pin. P64oe = 1 P6.4 used as output pin.
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= 0 P6.4 used as input pin. P63oe = 1 P6.3 used as output pin. = 0 P6.3 used as input pin. P62oe = 1 P6.2 used as output pin. = 0 P6.2 used as input pin. P61oe = 1 P6.1 used as output pin. = 0 P6.1 used as input pin. P60oe = 1 P6.0 used as output pin. = 0 P6.0 used as input pin.
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P17co = 1 Pin "P1.7" used as CMOS Output. = 0 Pin "P1.7" used as 8051 standard I/O. P16co = 1 Pin "P1.6" used as CMOS Output. = 0 Pin "P1.6" used as 8051 standard I/O. P15co = 1 Pin "P1.5" used as CMOS Output. = 0 Pin "P1.5" used as 8051 standard I/O. P14co = 1 Pin "P1.4" used as CMOS Output. = 0 Pin "P1.4" used as 8051 standard I/O. P13co = 1 Pin "P1.3" used as CMOS Output. = 0 Pin "P1.3" used as 8051 standard I/O. P12co = 1 Pin "P1.2" used as CMOS Output.
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= 0 Pin "P1.2" used as 8051 standard I/O.
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P11co = 1 Pin "P1.1" used as CMOS Output. = 0 Pin "P1.1" used as 8051 standard I/O. P10co = 1 Pin "P1.0" used as CMOS Output. = 0 Pin "P1.0" used as 8051 standard I/O. OPT (w):Configuration of chip optional, all standing for "0" in Chip Reset PWMf = 1 Selection of 94KHz PWM frequency = 0 Selection of 47KHz PWM frequency PWMd = 1 PWM pulse width for 253-step resolution = 0 PWM pulse width for 256-step resolution CPUclk = 1 CPU working at double rate = 0 CPU working at normal rate HSCLlo = 1 Enable slave I2C block to keep HSCL pin low in case of STK6006 being unable to catch up with the external master's speed MI2CS = 1 Master I2C block connected to HSCL/HSDA pins = 0 Master I2C block connected to ISCL/ISDA pins
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MI2CF1,MI2CF0 = 1,1 400KHz Master I2C frequency is selected = 1,0 200KHz Master I C frequency is selected
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= 0,1 50KHz Master I2C frequency is selected = 0,0 100KHz Master I2C frequency is selected 8.4 I/O Port 8.4.1 Port 1 Port 1, a group of pseudo-open drain pins or CMOS output pins selected by corresponding P1(n)co, can be used as general purpose I/O. The performance of port 1 is the same as 8051 standard if corresponding P1(n)co bit is cleared. 8.4.2 P3.0-2, P3.4-5 If these pins are not set as I2C pins, Port 3 can be applied as general purpose I/O, interrupt, UART and Timer pins. The performance of Port 3 is the same as 8051 standard. 8.4.3 Port 4, Port 5 and, Port 6 Port 5 and Port 6 are used as general purpose I/O, other than port 4 for real output. S/W is needed to set the corresponding P5(n)oe and P6(n)oe to explain whether all these pins are input or output.
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Reg. Name PORT4 PORT4 PORT4 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 Addr. F58h(w) F59h(w) F5Ah(w) F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) F3Fh(r/w) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P40 P41 P42 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67
PORT4 (w): data output value of port 4
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PORT5 (r/w): data input/output value of port 5 PORT6 (r/w): data input/output value of port 6. 8.5 PWM DAC Each 8 bits of PWMDA register in XFR control each output pulse width of PWM DAC converter. PWMf selects the frequency of PWM clock as 47KHz or 94KHz, and PWMd selects the total duty cycle step of these DAC outputs as 253 or 256. In case of PWMd=1, writing FDH/FEH/FFH to DAC register makes output stably high. Writing 00H to DAC register makes the output stably low. Reg. Name PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA
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Addr. F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F26h(r/w) F27h(r/w) F28h(r/w) F29h(r/w) F2Ah(r/w)
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10
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Bit 1
Bit 0
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STK6006
PWMDA PWMDA PWMDA F2Bh(r/w) F2Ch(r/w) F2Dh(r/w) Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13
PWMDA (r/w):The mentioned-above output pulse width control is used for DA0-13. * All of PWM DAC converters, after powered on, center on value 80h. 8.6 HSYNC /VSYNC Processing HSYNC/VSYNC processing block functions as a composite signal separation/insertion, H/V sync inputs presence check, a frequency counting, a polarity detection and control, together with a protection of the VBLANK output while VSYNC accelerates in a high clock rate of the DDC communication. The HSYNC present and frequency function block, depending on a digital filter, keep any pulse longer than the specified time period as pulse; the specified time period is under control of bits HDF1 and HDF0. However, the VSYNC digital filter without control bit operates as (HDF1, HDF0) =(0,0) of HSYNC.
Digital Filter
10Hz ~ 40Hz Check
Vpre
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Polarity Check & Freq. Count CVSYNC VSYNC
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Vpol XOR Vself VBpol XOR VBLANK
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10Hz ~ 40Hz Check
CVpre
Sync Separator
Digital Filter
Polarity Check & Freq. Count 10Hz ~ 10KHz Check
HC Hpol
Hpre HBpol
Composite Pulse Insert HSYNC
XOR Hself
XOR
HBLANK
H/V SYNC Processor Block Diagram
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8.6.1 H/V Frequency Counter
It is nice that the STK6006 can tell HSYNC frequency and VSYNC frequency and save the information in XFRs. We are sure that 14 bits of the Hcounter counts the time of 64*HSYNC period and then stores the result into an HCNT latch. When VSYNC/CVSYNC appears, the output value as [(128000000/H-Freq.)-1 is renewed per VSYNC/CVSYNC period, or else continuously renewed when VSYNC/CVSYNC disappear. 12 bits of the Vcounter counts the time between the two VSYNC pulses and then stores the result into a VCNT latch. Furthermore, per VSYNC/CVSYNC period the output value as (62500/V-Freq.) is renewed. An additional overflow bit means that H/V counter overflows; the change or overflow of VCNT/HCNT value will set the IVC/IHC interrupt. For more information in detail, please see the HCNT/VCNT value under the operation at 12MHz in Table 8.6.2.1 and Table 8.6.2.2. 8.6.2 Composite SYNC Separation/Insertion The input HSYNC is continuously controlled by STK6006. Once the VSYNC pulse is extracted from the HSYNC input, a Cvpre flag will be set and users can select the extracted "CVSYNC" for the sources of polarity check, frequency count, and VBLANK output. In comparison with the original signal, the CVSYNC has an 8s delay time. Also, the STK6006, during the active time of composite VSYNC, can insert pulse to HBLANK
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output. The width of inserted pulse counts up 1/8 HSYNC period and the inserted frequency can be
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corresponding to the original HSYNC. When "HinsB" control bit is set, the inserted pulse of HBLANK will be disabled, if "HinsB" is set to "1", then HBLANK output will be equal to HSYNC input. A polarity can surely be controlled by HBpol bit. 8.6.2.1 Horizontal Frequency table H-Freq(KHz) 1 2 3 4 5 6 7 8 9 10 11 12 31.5 37.5 43.3 46.9 53.7 60.0 68.7 75.0 80.0 85.9 93.8 106.3 14-bit Output Value 12MHz-OSC (hex/dec) 0FDEh / 4062 0D54h / 3412 0B8Bh / 2955 0AA8h / 2728 094Fh / 2383 0854h / 2132 0746h / 1862 06AAh / 1706 063Fh / 1599 05D1h / 1489 0554h / 1364 04B3h / 1203
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8.6.2.2 Vertical Frequency table V-Freq (Hz)
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12-bit Output Value 12MHz-OSC (hex/dec) 45Ch / 1116
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2 3 4 5 6 60 70 72 75 85 411h / 1041 37Ch / 892 364h / 868 341h / 833 2DFh / 735
8.6.3 Output HBLANK/VBLANK Control and Polarity Adjustment HBLANK is a mux output of the HSYNC, composite Hsync and self-test horizontal pattern; VBLANK is a mux output of the VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity are S/W controllable. If the frequency of VSYNC exceeds 250Hz, then the VBLANK output will be cut off. The HBLANK/VBLANK and P4.1/P4.0 share the output pin together.
8.6.4 Detection of H/V Polarity The polarity functions can detect a high and low pulse duty cycle of the input HSYNC/VSYNC. If the time width of high pulse is longer than that of low pulse, a negative polarity will be asserted; if not, a positive polarity, asserted. The change of Hpol value will set the IHpol interrupt; the change of Vpol will set the IVpol interrupt.
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8.6.5 Self-Test Pattern Generator STK6006 is able to generate various free-running timings with full white and full black patterns. User can properly set the content of the dot counters, DCNT, to get the free-running HBLANK frequency, and set the content of the line counters, LCNT, to get the free-running VBLANK frequency. The HBLANK/VBLANK pulse width, video front porch, and video back porch are controlled by PAT_HPUS, PAT_HBPO, PAT_HACT, PAT_VFPO, PAT_VPUS, and PAT_VBPO registers. The self-test pattern generator supports monitor manufacturer to do burn-in test, or offers end-user a reference to check the monitor. The output STO of the generator shares the output pin with P4.2.
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Full white (with black frame)
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STK6006
PAT_HAC
Hor.
PAT_HBPO PAT_HPUS
DCNT
Vert.
PAT_VBPO PAT_VPUS
PAT_VFPO
LCNT
8.6.6 Real-Time Check on H/V The Hpresent function checks the input HSYNC pulse, while the HSYNC rating above 10KHz will set the Hpre
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flag or if HSYNC raiting below 10Hz will clear the flag. Similarly, the Vpresent function checks the input
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VSYNC pulse, while the VSYNC rating above 40Hz will set the Vpre flag or if VSYNC rating below 10Hz will clear the flag. The change of Hpre value will set the IHpre interrupt; the change of Vpre/C Vpre will set the IVpre interrupt. 8.6.7 VSYNC Interrupt The STK6006 monitors the VSYNC input pulse and generates an interrupt on its leading edge. The VSYNC flag is set each time when STK6006 detects a VSYNC pulse. The flag will be cleared if S/W writes a "0". 8.6.8 HSYNC Clamp Pulse Output Setting an "HCLPE" control bit enables the HCLAMP output. The leading-edge position, pulse width, and polarity of HCLAMP are regarded as S/W controllable. 8.6.9 HSYNC /VSYNC Processing Register Reg. Name HVSTUS HCNT HCNT VCNT VCNT
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Addr. F40h(r) F41h(r) F42h(r) F43h(r) F44h(r)
Bit 7 CVpre HCovf HC7 VCovf VC7
Bit 6
HC6 VC6
Bit 5 Hpol HC13 HC5 VC5
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Bit 4 Vpol HC12 HC4 VC4
Bit 3 Hpre HC11 HC3 VC11 VC3
Bit 2 Vpre HC10 HC2 VC10 VC2
Bit 1 Hoff HC9 HC1 VC9 VC1
Bit 0 Voff HC8 HC0 VC8 VC0
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STK6006
HVCTR F40h(w) HVSELF F42h(w) HCLAMP F43h(w) HDF F44h(w) INTFLG F48h(r/w ) INTEN F49h(w) DCNT F60h(w) DCNT F61h(w) PAT_HACT F62h(w) PAT_HACT F63h(w) PAT_HPUS F64h(w) PAT_HBPO F65h(w) LCNT F66h(w) LCNT PAT_VFPO PAT_VPUS PAT_VBPO F67h(w) F68h(w) F69h(w) F6Ah(w) C1 HinsB HBpol ESelft RT CLPEG CLPPO CLPW2 CLPW1 CLPW0 HDF1 IVpre IHpol IVpol IHC IVC EIHC EIVC DCNT9 DCNT1 HACT9 HACT1 HPUS1 HBPO1 LCNT9 LCNT1 VFPO1 VPUS1 VBPO1 C0 VBpol INTL HDF0 IVsync EIVsync DCNT8 DCNT0 HACT8 HACT0 HPUS0 HBPO0 LCNT8 LCNT0 VFPO0 VPUS0 VBPO0
IHpre
EIHpre EIVpre EIHpol EIVpol
DCNT7 DCNT6 DCNT5 DCNT4 DCNT3 DCNT2 HACT7 HACT6 HACT5 HACT4 HACT3 HACT2 HPUS7 HPUS6 HPUS5 HPUS4 HPUS3 HPUS2 HBPO7 HBPO6 HBPO5 HBPO4 HBPO3 HBPO2 LCNT1 0 LCNT7 LCNT6 LCNT5 LCNT4 LCNT3 LCNT2 VFPO7 VFPO6 VFPO5 VFPO4 VFPO3 VFPO2 VPUS7 VPUS6 VPUS5 VPUS4 VPUS3 VPUS2 VBPO7 VBPO6 VBPO5 VBPO4 VBPO3 VBPO2
HVSTUS (r) : A status of the polarity, present, and static level in HSYNC and VSYNC.
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Hpol = 1 HSYNC input in positive polarity .com = 0 HSYNC input negative polarity Vpol = 1 VSYNC (CVSYNC) in positive polarity = 0 VSYNC (CVSYNC) in negative polarity Hoff = 1 Off-level of HSYNC input keeping high in case of Hpre=0 or Vpre=0 = 0 Off-level of HSYNC input keeping low in case of Hpre=0 or Vpre=0 Voff = 1 Off-level of VSYNC input keeping high = 0 Off-level of VSYNC input keeping low Hpre = 1 HSYNC input present = 0 HSYNC input not present Vpre = 1 VSYNC input present = 0 VSYNC input not present CVpre = 1 An extracted CVSYNC present = 0 An extracted CVSYNC not present HCNT (r): H-Freq counter HCovf = 1 H-Freq counter is overflowed; this bit is cleared by H/W when this condition is removed. HC13 - 0: 14 bits of H-Freq counter.
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VCNT (r): V-Freq counter VCovf = 1 V-Freq counter is overflowed; this bit is cleared by H/W when this condition is removed. VC11 - 0: 12 high bits of V-Freq counter HVCTR (w): H/V SYNC processor control register C1, C0 = 1,1 To select CVSYNC as a polarity, freq, and VBLANK source. = 1,0 To select VSYNC as a polarity, freq, and VBLANK source = 0,0 To disable a composite function = 0,1 H/W automatically switching to CVSYNC in case of CVpre=1 and VSpre=0 HinsB = 1 HBLANK without any insert pulse in composite mode = 0 HBLANK with an insert pulse in composite mode HBpol = 1 HBLANK output in negative polarity = 0 HBLANK output in positive polarity VBpol = 1 VBLANK output in negative polarity = 0 VBLANK output in positive polarity HVSELF (w): Self-test pattern generator control register Eselft = 1 To enable the generator = 0 To disable the generator RT = 1 An output in a full white pattern = 0 An output in a full black pattern INTL = 1 Interlace mode = 0 Non-interlace mode HCLAMP (w): HSYNC clamp pulse control register CLPEG = 1 Clamp pulse corresponding to a leading edge of the HSYNC = 0 Clamp pulse corresponding to a trailing edge of the HSYNC CLPPO = 1 Clamp pulse output in a positive polarity = 0 Clamp pulse output in a negative polarity CLPW2: CLPW0 : Pulse width of clamp pulse gained by [(CLPW2:CLPW0) + 1] x 0.167 s for 12MHz X'tal selection HDF (w): HSYNC digital filter control register. HDF1, HDF0 : = 0,0 To make any HSYNC pulse shorter than one OSC period (83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown region, and longer than two OSC period
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(166.67ns) as pulse
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= 0,1 To treat any HSYNC pulse shorter than half OSC period (41.66ns) as noise, between half and one OSC period (41.66ns to 83.33ns) as unknown region, and longer than one OSC period (83.33ns) as pulse = 1,x To Disable the digital filter for HSYNC INTFLG (w) : An Interrupt flag. An interrupt event will set its individual flag; a zero level will drive the INT1 source of 8051 core if the corresponding interrupt enable bit is set. Seriously, while serving the interrupt routine, software must clear this register. IHpre = 1 No operation. = 0 To clear the HSYNC presence change flag. IVpre = 1 No operation. = 0 To clear the VSYNC presence change flag. IHpol = 1 No operation. = 0 To clear the HSYNC polarity change flag. IVpol = 1 No operation. = 0 To clear the VSYNC polarity change flag.
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IHC = 1 No operation. IVC = 1 No operation.
= 0 To clear the HSYNC frequency change flag. = 0 To clear the VSYNC frequency change flag. IVsync = 1 No operation. = 0 To clear the VSYNC interrupt flag. INTFLG (r): Interrupt flag. IHpre = 1 To indicate an HSYNC presence change. IVpre = 1 To indicate a VSYNC presence change. IHpol = 1 To indicate an HSYNC polarity change. IVpol = 1 To indicate a VSYNC polarity change.
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IHC = 1 To indicate an HSYNC frequency change or counter overflow. IVC = 1 To indicate a VSYNC frequency change or counter overflow. IVsync = 1 To indicate a VSYNC interrupt. INTEN (w): Interrupt enable. EIHpre = 1 To enable the HSYNC presence change interrupt. EIVpre = 1 To enable the VSYNC presence change interrupt. EIHpol = 1 To enable the HSYNC polarity change interrupt.
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EIVpol = 1 To enable the VSYNC polarity change interrupt.
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STK6006
EIHC = 1 To enable the HSYNC frequency change / counter overflow interrupt. EIVC = 1 To enable the VSYNC frequency change / counter overflow interrupt. EIVsync = 1 To enable the VSYNC interrupt. DCNT (w): Dot divider in self-test pattern to get HBLANK output frequency. DCNT9 - 0: HBLANK freq. = X'tal freq. / (DCNT9 - 0). The valid range is 15KHz to 150KHz. For example, if 12MHz X'tal is used and 100KHz free-running HBLANK frequency is wanted, then the following dot divider content will be set DCNT = 12MHz / 100KHz = 120(dec) = 78(hex) PAT_HACT (w): Horizontal active region dot number of self-test pattern output. Dot frequency = X'tal freq. PAT_HPUS (w): HBLANK pulse width dot number of self-test pattern output. Dot frequency = X'tal freq. PAT_HBPO (w): Horizontal back porch dot number of self-test pattern output. Dot frequency = X'tal freq. LCNT (w): Line divider in self-test pattern to get VBLANK output frequency.
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LCNT10 - 0: VBLANK freq. = HBLANK freq. / (LCNT10 - 0). For example, if 100Hz free-running VBLANK frequency is wanted at HBLANK frequency = 100KHz, then the following line divider content will be set LCNT = 100KHz / 100Hz = 1000(dec) = 3E8(hex) PAT_VFPO (w): Vertical front porch line number of self-test pattern output. PAT_VPUS (w): VBLANK pulse width line number of self-test pattern output. PAT_VBPO (w): Vertical back porch line number of self-test pattern output. 8.7 DDC & I2C Interface 8.7.1 SlaveB Block Connected to HSDA and HSCL pins, the SlaveB I2C block can access the data using the I2C protocols. S/W may write the SLVBADR register to define the slave address. The SlaveB block in a receiving mode first detects an I2C slave address matching the condition and then issues an ISlvBM interrupt. When a data byte is received, the data received from HSDA is transited into the shift register and then written to the RCBBUF register; the first data written in RCBBUF is a word address,
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and the slave address is dropped. Once the RCBBUF is written in every time, this block generates an IRCB
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STK6006
interrupt (RCBBUF full interrupt). However, if software cannot in time read out the RCBBUF, the next byte in shift register is naturally not loaded into the RCBBUF and the SlaveB block sends NACK back to the master. The WadrB flag can determine for software whether the data in RCBBUF is a word address or not. Similarly, the block in a transmitting mode first detects an I2C slave address matching the condition, and then issues an ISlvBM interrupt, while the data loaded in the TXBBUF is written to the shift register every time, which results in an empty TXBBUF and generates a ITXB interrupt (TXBBUF empty interrupt). Before an empty shift register is formed, S/W should write a new byte to the TXBBUF for the next transfer. Writing "0" to a corresponding bit in the INTFLG register clears the ISlvBM; reading RCBBUF out clears the IRCB; writing TXBBUF clears the ITXB. If you want to learn more about " Slave I2C Block Timing", please refer to the attachment. 8.7.2 DDC1/DDC2x Mode, DDCRAM, and SlaveA Block After reset, the STK6006 exists in the DDC1 mode, and then VSYNC is used as a data clock. The HSCL pin should keep at a high level. the data output to the HSDA is accessed from a shift register in the STK6006; the shift register automatically fetches an EDID data from the lower 128-byte Dual Port RAM (DDCRAM), and sends it in 9 bits of a pocket format together with a null bit (=1) as a pocket separator. By way of
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setting/clearing the EDDC1 control bit, software may enable/disable DDC1 function. .com Detecting a high-to-low transition on the HSCL pin, the STK6006 switches to a DDC2x mode. In this mode, the SlaveA I2C block automatically transmits/receives the data to /from the I2C Master. The accessed data is taken from the DDCRAM and/or saved to the DDCRAM; namely, the STK6006 can operate as 24LC02 EEPROM. S/W writes only the EDID data to DDCRAM, so S/W can select the slave address of SlaveA block as 5-bit, 6-bit, or 7-bit one. Let's take it for example that if S/W selects a 5-bit slave address as 10100b, then the SlaveA I2C block answers to slave address 10100xxb. Setting/clearing the ESlvA bit can enable/disable the SlaveA. By means of setting/clearing the EW128/EW256 bit, the I2C Master may freely write the lower/upper DDCRAM. In addition, if the only only128 control bits are set, the SlaveA accesses only the lower 128-byte DDCRAM. If HSCL is kept high for 128 VSYNC periods, then the STK6006 goes back to the DDC1 mode. Having been detected on an HSCL/HSDA bus, a valid I2C address (1010xxxb) locks in a DDC2B mode; therefore, the DDC2 flag reflecting the present DDC status, S/W may clear it by writing a "0" to it. 8.7.3 I2C Function Block in Master Mode The selection of a MI2CS control bit may have the I2C block in the master mode connected to the ISDA/ISCL pins, in which, its speed ranging from 50KHz to 400KHz when software sets up the MI2CF1/MI2CF0 control bit. Through this interface the S/W program can access the external I2C device. The master I2C access process is summarized as follows:
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8.7.3.1. To read the I2C Device 1. Write the Slave Address to MBUF. 2. Set S bit to Start. 3. The STK6006 transmitting this byte, an IMbuf interrupt is triggered. 4. Set or reset the MAckO flag with respect to the I2C protocol. 5. Read the useless byte out of MBUF to continue the data transfer. 6. The STK6006 receiving a new byte, the IMbuf interrupt is once more triggered. 7. Read MBUF will trigger the next receiving operation, but set P bit before read will stop I2C operation. 8.7.3.2. To write the I2C Device 1. Write the Slave Address to MBUF. 2. Set S bit to Start. 3. The STK6006 transmitting this byte, an IMbuf interrupt is triggered. 4. Programs can write MBUF to transfer a next byte or to set P bit to stop. Reg. Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CCTR F00h (r/w) DDC2 MAckO P S .com I2CSTUS F01h (r) WadrB SlvRWB SAckIn SLVS MackIn INTFLG F03h (r) ITXB IRCB ISlvBM ISTOP IReSta IWSlvA IMbuf INTFLG F03h (w) ISlvBM ISTOP IReSta IWSlvA IMbuf INTEN F04h (w) EITXB EIRCB EISlvB EISTOP EIReSta EIWSlv EIMbuf M A MBUF F05h (r/w) Master I2C receive/transmit data buffer DDCCTR F06h (w) EDDC EW128 EW256 Only128 SlvAs1 SlvAs0 1 SLVAADR F07h (w) ESlvA I2C Slave A address 2 RCBBUF F08h (r) I C Slave B receiving buffer TXBBUF F08h (w) I2C Slave B transmitting buffer SLVBADR F09h (w) ESlvB I2C Slave B address IICCTR (w): I2C interface control register. DDC2 = 0 Force STK6006 back to the DDC1 mode from the DDC2 mode MackO = 1 NACK will be returned by STK6006 in the master receiving mode = 0 ACK will be returned by STK6006 in the master receiving mode S, P = , 0 Start condition in case of Master I2C being not during transfer = X, Stop condition in case of Master I2C being not during transfer = 1, X Resume transfer after a read/write MBUF operation IICCTR (r): I2C interface status register. DDC2 = 1 DDC2 active
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= 0 STK6006 in the DDC1 mode IICSTUS (r) : I2C interface status register. WadrB = 1 The data in RCBBUF used as word address SlvRWB = 1 Current transfer used as slave transmit = 0 Current transfer used as slave receive SAckIn = 1 The external I2C host responding NACK = 0 The external I2C host responding ACK SLVS = 1 The slave block having detected a START, but cleared it when STOP detected MAckIn = 1 NACK received from the slave I2C device in Master I2C = 0 ACK received from the slave I2C device in Master I2C INTFLG (w): Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, a zero level will drive the 8051 INT1 source. Software is necessary to clear this register while serving the interrupt routine. ISlvBM= 1 No operation.
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= 0 To clear the ISlvBM flag. ISTOP= 1 No operation. = 0 To clear the ISTOP flag. IReSta = 1 No operation. = 0 To clear the IReSta flag. IWSlvA = 1 No operation. = 0 To clear the IWSlvA flag. IMbuf= 1 No operation.
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= 0 To clear the Master I2C bus interrupt flag (IMbuf). INTFLG (r): Interrupt flag. ITXB = 1 To indicate the TXBBUF needs a new data byte, cleared by writing TXBBUF. IRCB = 1 To indicate the RCBBUF has received a new data byte, cleared by reading RCBBUF. ISlvBM = 1 To indicate the slave I2C address B match condition. ISTOP = 1 To indicate the slave I2C has detected a STOP condition. IReSta = 1 To indicate the slave I2C has detected a repeated START condition. IWSlvA = 1 To indicate the slave A I2C has detected a STOP condition in write mode. IMbuf = 1 To indicate a byte is sent to and/or received from the master I2C bus. INTEN (w): Interrupt enable.
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EITXB= 1 To enable the TXBBUF interrupt.
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EIRCB= 1 To enable the RCBBUF interrupt. EISlvBM = 1 To enable the slave address B match interrupt. EISTOP = 1 To enable the I2C bus STOP interrupt. EIReSta = 1 To enable the I2C bus repeated START interrupt. EIWSlvA = 1 To enable the slave A I2C bus STOP of interrupt in write mode EIMbuf= 1 To enable the Master I2C bus interrupt. Mbuf (w) : STK6006's transmission to the I2C bus. Mbuf (r) : Master I2C data shift register; after START and before STOP condition, reading this register resumes STK6006's reception from the I2C bus DDCCTR (w): DDC interface control register. EDDC1 = 1 To enable the DDC1 data transfer in DDC1 mode.
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Master I2C data shift register; after START and before STOP condition, writing this register resumes
= 0 To disable the DDC1 data transfer in DDC1 mode. EW128 = 1 To indicate that I2C master can write the lower 128-byte(00-7F) DDCRAM = 0 To indicate that I2C master can not write the lower 128-byte(00-7F) DDCRAM EW256 = 1 To indicate that I2C master can write the higher 128-byte(80-FF) DDCRAM = 0 To indicate that I2C master can not write the higher 128-byte(80-FF) DDCRAM Only128 = 1 To indicate that the SlaveA always accesses EDID data from the lower 128-byte of DDCRAM = 0 To indicate that the SlaveA accesses EDID data from the complete 256-byte of DDCRAM SlvAs1,SlvAs0 : Slave I2C block A's slave address length. = 1,0 5 bits of the slave address. = 0,1 6 bits of the slave address. = 0,0 7 bits of the slave address. SLVAADR (w): Slave I2C block A's enable and address. ESlvA = 1 To enable slave I2C block A. = 0 To disable slave I2C block A. bit6-0: Slave I2C address A where the slave block should respond RCBBUF (r): Slave I2C block B receiving the data buffer TXBBUF (w): Slave I2C block B transmitting the data buffer
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STK6006
SLVBADR (w): Slave I2C block B's enable and address. ESlvB = 1 To enable slave I2C block B. = 0 To disable slave I2C block B. bit6-0 : Slave I2C address B where the slave block should respond 8.8 A/D converter Installed with four 6-bit A/D converters in VDD ranges is the STK6006. Software can choose a current converting channel by setting the SAD3/SAD2/SAD1/SAD0 bits. The refresh rate of the ADC may be gained by OSC freq./1536 (128s for 12MHz crystal). The voltage on the input pin is compared with the voltage on the internal VDD x N / 64, where N=0-63, by the ADC. The ADC output value is N when pin voltage is higher than VDD x N / 64 and lower than VDD x (N+1) / 64. Reg. Name Addr. Bit 7 ADC F10h (r) ADC F10h (w) EADC ADC (w): ADC control. ENADC= 1 To enable the ADC. SADC0= 1 To select the ADC0 pin input. SADC1= 1 To select the ADC1 pin input. SADC2= 1 To select the ADC2 pin input. SADC3= 1 To select the ADC3 pin input. ADC (r): ADC converting result 8.9 Low Power Reset (LVR) & Watchdog Timer The Low Power Reset rise a chip reset signal when the voltage level of power supply goes below 3.8V / 2.5V in 5V / 3.3V system in a specific period of time. After the voltage level of power supply rise above 3.8V / 2.5V in 5V/3.3V system, LVR stays at a reset state for 414 crystal cycles to make sure the chip exits from reset condition with a stable crystal oscillation. When Watchdog Timer is overflowed, it automatically ensures a device reset. The overflow interval is gained by 0.25 sec x N, in which N is a number ranging from 1 to 8, and it can be programmed by way of register WDT2-0. Since the timer function is disabled after power-on reset, users may enable this function by setting EWDT and clear the timer by setting WDTclr. Reg. Name
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Bit 6
Bit 5
Bit 4
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Bit 3 Bit 2 Bit 1 ADC converting result SAD3 SAD2 SAD1
Bit 0 SAD0
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Addr.
Bit 7
Bit 6
Bit 5
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Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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WDT F18h (w) EWDT WDTclr WDT2 WDT1 WDT0
WDT (w): Watchdog Timer control register. EWDT = 1 To enable the Watchdog Timer WDTclr = 1 To clear the Watchdog Timer WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec. = 1 Overflow interval = 1 x 0.25 sec. = 2 Overflow interval = 2 x 0.25 sec. = 3 Overflow interval = 3 x 0.25 sec. = 4 Overflow interval = 4 x 0.25 sec. = 5 Overflow interval = 5 x 0.25 sec. = 6 Overflow interval = 6 x 0.25 sec. = 7 Overflow interval = 7 x 0.25 sec. 8.10 In-System Programming Function (ISP) The features of ISP are outlined as below: 1. Block Erase: 128 Byte, 10mS
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2. Whole Flash erase: 100mS
3. Byte programming Cycle time: 40uS per byte 5. CRC check.
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4. Whole 64K-byte Flash programming within 6 Sec. After Power On/Reset, The STK6006 runs the original Program Code. Once the S/W detects an ISP request, S/W can accept the request following the steps below: 1. Clear watchdog and disable all interrupt. 2. Write ISP control block slave address to ISPSLV. 3. Write 93h to ISP enable register (ISPEN) to enable ISP. 4. Enter 8051 idle mode immediately. When ISP is enabled, the STK6006 enter into ISP mode in 15-22.5uS. In the mode, PWM DACs and I/O pins keep running at their former status. Reg. Name Addr. ISPSLV F0Bh(w) ISPEN F0Ch(w) 8.10.1 ISP Control Block STK6006 built in a ISP control block, that is a I2C slave device. By this block, user can treats the 64K-byte Flash as 32 EEPROM (like as 24C16, called "EEPROM_like" in this data sheet). There are two type of I2C bus transfer in this block:
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Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 ISP Control Block Slave Address Write 93h to enable the ISP mode
Bit 1
Bit 0
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STK6006
Write: Read: Where S = start ttttttt = ISP Control Block Slave Address k = ack by slave dddddddd = data CCCCCCCC = crc_register[15:8] Addr. 00h(w) 01h(w) 02h(w) 00h(w): SDP = 1 To enable the S/W data protection of Flash. User needs to set this bit in the end of ISP mode. SDUP = 1 To disable the S/W data protection of Flash. User needs to set this bit in the start of ISP mode. ERASE = 1 To erase one page (128-byte) of Flash.
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S-ttttttt0k-000000wwk-ddddddddk-P S-ttttttt1k-CCCCCCCCK-ccccccccK-P P = stop ww = word address K = ack by host ( 0 or 1) cccccccc = crc_register[7:0]
Bit 7 SDP
Bit 6 SDUP
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERASE BLANK CRCclr CPUclr BANK4 BANK3 BANK2 BANK1 BANK0 EPSadr
BLANK = 1 To erase whole Flash. CRCclr = 1 To clear CRC register. CPUclr = 1 To reset STK6006.
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Above 6 bits will be clear by I2C STOP condition. And only one bit can be set to 1 at the same time. 01h(w): BANK4 - 0 : EEPROM_like bank selection. Choice any one of EEPROM_like to access. 02h(w): EPSladr : EEPROM_like slave address. 8.10.2 Start to ISP Data Write/Read In STK6006, the ISP function works following the step below: 1. Define EEPROM_like slave address. 2. Set SDUP bit to disable Flash soft-ware data protection. 3. Set CRCclr bit to reset CRC_register. 4. Define the bank of EEPROM_like. 5. Set ERASE/BLANK bit to block-erase/chip-erase Flash. 6. Access EEPROM_like as standard EEPROM. 7. Check CRC_register. 8. Set SDP bit to enable Flash soft-ware data protection. 9. Set CPUclr bit to reset STK6006.
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STK6006
The step between 4 and 6 are re-cycled until all data are written into Flash. There are four type of I2C bus transfer in EEPROM_like: Byte Write: S-ttttAAA0-k-wwwwwwww-k-dddddddd-k-P Page Write: S-ttttAAA0-k-wwwwwwww-k-dddddddd-k-dddddddd-k... -P ... Random Read: S-ttttAAA0-k-wwwwwwww-k(-P)-S-ttttAAA1-k-dddddddd-K-P Sequential Read: S-ttttAAA0-k-wwwwwwww-k(-P)-S-ttttAAA1-k-dddddddd-K-dddddddd-K-P Where S = start or re-start tttt = EEPROM_like Slave Address AAA = page block address k = ack by slave dddddddd = data The word address automatically increases every time when data byte is transferred. The page size is
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P = stop wwwwwwww = word address K = ack by host ( 0 or 1)
256-byte.
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In STK6006 Flash memory, the program cycle time is 40us. If the ISP slave is not able to complete the program cycle in time, it returns non-ack to the following data byte. In the meantime, the word address does not increase and the CRC does not count the non-acked data byte. 8.10.3 Cyclic Redundancy Check (CRC)
The ISP Host is able to read the ISP Control Block directly to get the CRC value, instead of reading
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each byte in Flash. The CRC register counts each data byte acknowledged by the ISP slave during data program period. All bits "1" will be loaded into 16 bits of the CRC register by setting CRCclr bit. Msb is the data byte first shifted into the CRC register.
CRCin = CRC[15]^DATAin; CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin}; Where^ = XOR example: data_byte F6H 28H C3H
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CRC_register_remainder FFFFH FF36H 34F2H 7031H
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STK6006 9. MEMORY MAP of XFR
Reg. Name Addr. Bit 7 Bit 6 IICCTR F00h (r/w) DDC2 IICSTUS F01h (r) WadrB INTFLG F03h (r) ITXB IRCB INTFLG F03h (w) INTEN F04h (w) EITXB EIRCB MBUF DDCCTR SLVAADR RCBBUF TXBBUF SLVBADR ISPSLV ISPEN ADC ADC WDT PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PWMDA PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 F05h (r/w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) F0Bh(w) F0Ch(w) F10h (w) F10h (r) F18h (w) F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F26h(r/w) F27h(r/w) F28h(r/w) F29h(r/w) F2Ah(r/w) F2Bh(r/w) F2Ch(r/w) F2Dh(r/w) F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) Bit 5 Bit 4 Bit 3 Bit 2 MAckO Bit 1 P SlvRWB SAckIn SLVS ISlvBM ISTOP IReSta IWSlvA ISlvBM ISTOP IReSta IWSlvA EISlvB EISTOP EIReSta EIWSlv M A Master IIC receives/transmits data buffer EDDC EW128 EW256 Only128 SlvAs1 SlvAs0 1 ESlvA Slave A I2C Address Slave B I2C receives buffer Slave B I2C transmits buffer ESlvB Slave B I2C Address ISP Control Block Slave Address Write 93h to enable the ISP mode ENAD SADC3 SADC2 SADC1 SADC0 C ADC Converting Result EWDT WDTclr WDT2 WDT1 WDT0 Pulse width of PWM DAC 0 .com of PWM DAC 1 Pulse width Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66
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Bit 0 S MackIn IMbuf IMbuf EmbufI
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STK6006
PORT6 F3Fh(r/w) P67 HVSTUS F40h(r) CVpre Hpol Vpol Hpre Vpre Hoff Voff HCNT F41h(r) Hovf HF13 HF12 HF11 HF10 HF9 HF8 HCNT F42h(r) HF7 HF6 HF5 HF4 HF3 HF2 HF1 HF0 VCNT F43h(r) Vovf VF11 VF10 VF9 VF8 VCNT F44h(r) VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0 HVCTR F40h(w) C1 C0 HinsB HBpol VBpol HVSELF F42h(w) ESelft RT INTL HCLAMP F43h(w) CLPEG CLPPO CLPW2 CLPW1 CLPW0 HDF F44h(w) HDF1 HDF0 INTFLG F48h(r/w) IHpre IVpre IHpol IVpol IHC IVC Vsync INTEN F49h(w) EIHpre EIVpre EIHpol EIVpol EHF EVF EVsync PADOPT F50h(w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E PADOPT F51h(w) P56E P55E P54E P53E P52E P51E P50E PADOPT F52h(w) HI2CE II2CE HCLPE P42E P41E P40E PADOPT F53h(w) P56oe P55oe P54oe P53oe P52oe P51oe P50oe PADOPT F54h(w) P67oe P66oe P65oe P64oe P63oe P62oe P61oe P60oe PADOPT F55h(w) P17co P16co P15co P14co P13co P12co P11co P10co OPT F56h(w) PWMf PWMd CPUclk HSCLlo MI2CS MI2CF1 MI2CF0 PORT4 F58h(w) P40 PORT4 F59h(w) P41 PORT4 F5Ah(w) P42 DCNT F60h(w) DCNT9 DCNT8 .com DCNT F61h(w) DCNT DCNT6 DCNT5 DCNT4 DCNT3 DCNT2 DCNT1 DCNT0 7 PAT_HACT F62h(w) HACT9 HACT8 PAT_HACT F63h(w) HACT HACT6 HACT5 HACT4 HACT3 HACT2 HACT1 HACT0 7 PAT_HPUS F64h(w) HPUS7 HPUS6 HPUS5 HPUS4 HPUS3 HPUS2 HPUS1 HPUS0 PAT_HBPO F65h(w) HBPO HBPO6 HBPO5 HBPO4 HBPO3 HBPO2 HBPO1 HBPO0 7 LCNT F66h(w) LCNT1 LCNT9 LCNT8 0 LCNT F67h(w) LCNT7 LCNT6 LCNT5 LCNT4 LCNT3 LCNT2 LCNT1 LCNT0 PAT_VFPO F68h(w) VFPO7 VFPO6 VFPO5 VFPO4 VFPO3 VFPO2 VFPO1 VFPO0 PAT_VPUS F69h(w) VPUS7 VPUS6 VPUS5 VPUS4 VPUS3 VPUS2 VPUS1 VPUS0 PAT_VBPO F6Ah(w) VBPO7 VBPO6 VBPO5 VBPO4 VBPO3 VBPO2 VBPO1 VBPO0
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DataShee
10. ELECTRICAL PARAMETERS
10.1 DC Characteristics Conditions at: Ta=0 ~ 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Conditions Output "L" Voltage Vol Iol=5mA Voh1 VDD=5V, Ioh=-50A Output "H" Voltage on 8051 I/O port pin
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Min. 4
Max. 0.45
Unit V V
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STK6006
Voh2 Output "H" Voltage on CMOS output Voh3 Voh4 Vil1 Vil2 Vih1 Vih2 Rrst Cio VDD=3.3V, Ioh=-50A VDD=5V, Ioh=-4mA VDD=3.3V, Ioh=-4mA VDD=5V VDD=3.3V VDD=5V VDD=3.3V VDD=5V 2.65 4 2.65 -0.3 -0.3 0.4 x VDD 0.6 x VDD 150 V V V 0.2 x VDD V 0.3 x VDD V VDD +0.3 V VDD +0.3 V 250 Kohm 15 pF
Input "L" Voltage Input "H" Voltage RST Pull Down Resistor Pin Capacitance 10.2 AC Characteristics
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Conditions at: Ta=0 ~ 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Conditions Min. Crystal Frequency fXtal PWM DAC Frequency fDA fXtal=12MHz 46.875 HSYNC input pulse Width tHIPW fXtal=12MHz 0.3 VSYNC input pulse Width tVIPW fXtal=12MHz 3 HSYNC to HBLANK output jitter tHHBJ H+V to VBLANK output delay tVVBD fXtal=12MHz CVSYNC pulse width in H+V signal tVCPW FXtal=12MHz 20 .com 10.3 Absolute Maximum Ratings Conditions at: Ta= 0 ~ 70 oC, VSS=0V Name Operating Temperature Storage Temperature Output Voltage Input Voltage (other pins) Supply Voltage Input Voltage (HSYNC, VSYNC & open-drain pins) 10.4 Operating Conditions Allowable Conditions at: Ta= 0 ~ 70 oC, VSS=0V Name Supply Voltage Operating Freq. Symbol VDD Fopg Conditions 5V system 3.3V system Min. 4.5 3.0 Symbol Topg Tstg Vout Vin2 VDD Vin1
Typ. 12
Max. 94.86 7.5 5
8
Unit MHz KHz s s ns s s
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Range 0 ~ +70 -25 ~ +125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ +6.0 -0.3 ~ 5V+0.3
Unit oC oC V V V V
Max. 5.5 3.6 15
Unit V V MHz
11. PACKAGE DIMENSION
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STK6006
11.1 40-Pin PDIP 600 Mil
52.197mm +/-0.127
1.981mm +/-0.254
1.270mm +/-0.254
0.457mm +/-0.127
2.540mm
15.494mm +/-0.254
13.868mm +/-0.102
1.778mm +/-0.127
0.254mm +/-0.102
3.81mm +/-0.127
3.302mm +/-0.254
0.254mm (min.)
5o~70
6o +/-3o 16.256mm +/-0.508
11.2 42-Pin SDIP Unit: mm
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Symbol Min A 3.937 A1 1.78 B1 0.914 D 36.78 E1 13.945 F 15.19 eB 15.24 c 0X
Dimension in mm
Nom 4.064 1.842 1.270 36.83 13.970 15.240 16.510 7.5X
Max 4.2 1.88 1.118 36.88 13.995 15.29 17.78 15X
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15.494mm +/0.254 13.868mm +/0.102
0.254 m +/-0.1
5o~7
0
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11.3 44-Pin PLCC Unit:
0.045*45 0 PIN #1 HOLE 0.180 MAX. 0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005 0.610 +/-0.02 0.653 +/-0.003 0.500
70TYP. 0.010 0.050 TYP. 0.026~0.032 TYP. 0.070 0.653 +/-0.003 0.690 +/-0.005 0.070
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12. Information
12.1 Order Information: Part No. STK6006-F1 STK6006-F2 STK6006-F3 Pin Count 40 42 44
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Package P-DIP S-DIP PLCC
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Marking
STK6006-F1 Manu. No STK6006-F2 Manu. No STK6006-F3 Manu. No
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Syntek Logo
12.2 Contact Information : If you need more details information or samples requested, PLS contact the next window then we will response you as soon as we can. OYb3/4EAeN/|- 1/2 q o|ae3/4P gz 1/4BFN qU Cu / / Kevin Liu : 528 / / Tel : 886 - 3-577-3181 Ext:528 Fax : 886 - 3-577-8010 / / Marketing Manager Syntek Semiconductor Co., Ltd. Marketing & Sales Dept.
: 886 - 3-577-3181 A3/4/ : 886 - 3-577-8010
E-mail : cjliu@syntekt.com.tw Mobile : 0936-060871
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